Forum Discussion
New ContributorResets being routed through CLKENA blocks and then not meeting Recovery timing
It's entirely possible for a high fanout control signal put on a global routing channel to have timing issues. Nothing unusual about taking it off the global as a possible solution (which seemed to work in your case). If you do want to use a global, you still could but you may need to check which clock control block is being used and adjust other global signal use using assignments like you did. The "insertion delay", the delay caused by routing the signal over to an available clock control block to get it onto the global routing channel, is usually the culprit. If you're design is already using some CCBs, it may have forced the Fitter to select one farther away, causing the issue.
Super ContributorIt's entirely possible for a high fanout control signal put on a global routing channel to have timing issues. Nothing unusual about taking it off the global as a possible solution (which seemed to work in your case). If you do want to use a global, you still could but you may need to check which clock control block is being used and adjust other global signal use using assignments like you did. The "insertion delay", the delay caused by routing the signal over to an available clock control block to get it onto the global routing channel, is usually the culprit. If you're design is already using some CCBs, it may have forced the Fitter to select one farther away, causing the issue.
SamWhiteCorrect, the issue was that the clock control block being used was on the opposite side of the chip to the logic it was resetting. I will bear your comment in mind, thanks.
