Reset_ip for stratix GX development board

Hello,

The Design Assistant rule CDC-50012 indicates that your synchronizer chain is being driven by signals from multiple clock domains. This violates the principle of proper CDC (Clock Domain Crossing) design, which requires each synchronizer chain to handle signals from only one clock domain.

From violation description, we can conclude that the synchronizer chain reset_reg[0] is being driven by internal_clk and its inverted counterpart (internal_clk (INVERTED)). This creates ambiguity in the source clock domain for the chain.

If your reset signal is generated in a clock domain (e.g., internal_clk) and used asynchronously in another domain (clk_in), you need to properly synchronize it to avoid CDC issues.

Please make sure the reset signal is synchronized to a single clock domain (internal_clk OR clk_in) before entering the synchronizer chain.

If internal_clk and clk_in must both contribute to the reset logic, use separate synchronizer chains for signals from each clock domain.

Example how to sync reset signal to internal_clk domain, then transfer to clk_in domain:

// Synchronize to internal_clk

reg sync_reset_internal_clk1, sync_reset_internal_clk2;

always @(posedge internal_clk or negedge async_reset)

if (!async_reset)

{sync_reset_internal_clk2, sync_reset_internal_clk1} <= 2'b00;

else

{sync_reset_internal_clk2, sync_reset_internal_clk1} <= {sync_reset_internal_clk1, async_reset};

// Transfer to clk_in domain

reg sync_reset_clk_in1, sync_reset_clk_in2;

always @(posedge clk_in or negedge sync_reset_internal_clk2)

if (!sync_reset_internal_clk2)

{sync_reset_clk_in2, sync_reset_clk_in1} <= 2'b00;

else

{sync_reset_clk_in2, sync_reset_clk_in1} <= {sync_reset_clk_in1, sync_reset_internal_clk2};

// Use sync_reset_clk_in2 in the clk_in domain

wire reset_out = sync_reset_clk_in2;

re-run the Design Assistant Report-> verify CDC-50012 violation is cleared.

regards,

Farabi