New ContributorReset_ip for stratix GX development board
Hello, could some one help me rectifying the issue with the usage of reset IP with Intel Stratix FPGA development board.
I am trying to understand how does this IP function when my design have an asynchronous reset. I have tried to create an 8-bit counter. I have uploaded the design files. The design is completely compiled. I have used a clock of 200MHZ(clk_in). However, the reset IP operated at 100MHZ internally. I have used a synchronizer chain to address the CDC issue here. Kindly check my design. Even though the design is getting compiled, DRC report still shows the rule violation CDC-50012 Multiple clock domain driving a synchronizer chain.
Design Assistant Document:
CDC-50012
Tags: synchronizer
Description:
A synchronizer chain is accepting data from multiple clock domains at once. A synchronizer chain can only synchronize data from a single clock domain.
Recommendation:
Either synchronize each incoming clock domain with different synchronizer chains in the same destination domain, placing any required combination al logic in the destination domain, or cascade the clock crossings with transfers from one source clock domain at a time.
Violation Fields Description:
'From' : Registers that launch data in a CDC transfer
'To' : Registers that latch data in a CDC transfer
'From Clock' : CDC transfer source clock(s). These clocks drive the "From" registers
'To Clock' : CDC transfer destination clock(s). These clocks drive the "To" registers
'Reason' : The reason why a transfer is considered a CDC
From : dut_test|s10_user_rst_clkgate_0|lsm_gpo_out_user_reset~internal_clock.reg dut_test|s10_user_rst_clkgate_0|lsm_gpo_out_user_reset~internal_clock.reg__nff
To: syn_test|reset_reg[0]
From clk: internal_clk internal_clk (INVERTED)
To clock: clk_in
Reason: Asynchronous transfer
I am unable to identify what went wrong here. I even tried to double flop the ninit_done signal before passing to the assign statement 'reset_out' (not shown in code). But this also is not rectifying the issue. If someone help me with what went wrong it would be beneficial. Thanks a lot for your time.
