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Altera_Forum
Honored Contributor
Honored ContributorReset for PLL
I am working on a project involving Arria V FPGA. I need to have a PLL for generating clocks for my internal FPGA logic. I am confused about the reset signal of PLL. I have no external H/W reset...
Altera_ForumHonored Contributor
Honored ContributorNo. I don't know that you can't rely on that setting - I'd have thought you can. Hence why you thought the warning isn't relevant - I see now.
Cheers, Alex
