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Altera_Forum's avatar
Altera_Forum
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10 years ago

Reset for PLL

I am working on a project involving Arria V FPGA. I need to have a PLL for generating clocks for my internal FPGA logic. I am confused about the reset signal of PLL. I have no external H/W reset...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

You can't call it an 'erroneous warning' - it's perfectly valid and simply draws you're attention to the possible issue. If you have a glitch on your clock or PSU that causes the PLL to lose lock then it may not recover without a reset.

If you have a mechanism whereby you can pulse the PLL reset in the event of the lock signal deactivating then you clearly should do so. If you don't then, as you say, you'll have to live with it. The question is how likely is the PLL to lose lock? Good question. However, if you have anything critical (in your mind) that can't cope with it losing lock then you need to design in a means of resetting it.

Cheers,

Alex