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Honored Contributor
Honored ContributorReset for PLL
I am working on a project involving Arria V FPGA. I need to have a PLL for generating clocks for my internal FPGA logic. I am confused about the reset signal of PLL. I have no external H/W reset...
Altera_ForumHonored Contributor
Honored ContributorDriving the PLL reset with it's own locked output signal (inverted) sounds reasonable to me. I've just tried this - Quartus allows this with Cyclone V. So, it caters for routing this.
Is it necessary? That depends on what you want to happen upon loss of lock. All registers are going to retain a static value should the clock stop due to loss of lock. Whether that's acceptable in your application is up to you. Cheers, Alex
