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Honored Contributor
Honored ContributorReset for PLL
I am working on a project involving Arria V FPGA. I need to have a PLL for generating clocks for my internal FPGA logic. I am confused about the reset signal of PLL. I have no external H/W reset...
Altera_ForumHonored Contributor
Honored ContributorIn a similar situation, I have no HW reset pin so I was planning to use loss of lock to drive a reset to the PLL, and also reset the all the registers in my design to a known state. Does it make sense to do that?
I'm wondering if it's even necessary to do this, but I've never coded an FPGA without a reset.
