Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorReset for PLL
I am working on a project involving Arria V FPGA. I need to have a PLL for generating clocks for my internal FPGA logic. I am confused about the reset signal of PLL. I have no external H/W reset...
Altera_ForumHonored Contributor
Honored ContributorHi Nagakiran,
The reset to PLL is important especially after the PLL lose lock, or there is any change to the refclk, or dynamic reconfiguration performed. You can create some user logic to control the reset when these three events occur.
