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Altera_Forum
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10 years ago

Reset for PLL

I am working on a project involving Arria V FPGA. I need to have a PLL for generating clocks for my internal FPGA logic. I am confused about the reset signal of PLL. I have no external H/W reset...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Having just checked (I assumed the same as Cris) it seems the reset input port is 'required' for the Altera PLL suitable for Arria V - see the user guide (https://www.altera.com/en_us/pdfs/literature/ug/altera_pll.pdf). A quick play with Quartus confirms this.

POR pin? There isn't one - only an internal POR circuit for the device. I don't think there's any access to it. So, if tying reset to '0' isn't sufficient and you must generate a reset, I suggest you consider a counter that generates a reset at power up. And, if the PLL ever looses lock you can consider resetting the counter to regenerate the reset.

Cheers,

Alex