Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorrerun EDA netlist writer
hi everyone, i just installed altera ver 8.1. started a new project. did RTL simulation. created SDC. but when i click on run gate level timing simulation on the tools menu, i keep getting an ...
SFlow
New Contributor
New ContributorI'm running on 17.1 and had the same error occur. I was able to resolve the issue by simply restarting compilation. Hope that can help someone
