Relative Timing of NSTATUS and CONF_DONE

I am using an Arria II GX FPGA (EP2AGX190) with a custom loader FPGA that transfers configuration data from a parallel flash device to the Arria II GX FPGA. I am using FPP mode to transfer the data using DCLK and the 8-bit data bus. CONF_DONE is connected to an external pull-up resistor per the datasheet guidelines.

I have the following question:

Are the two conditions mutually exclusive in time (will never occur at the same time):

1. The clearing (transition to logic 0) of NSTATUS (due to the Arria II detecting corrupt data on the very last CRC calculation during configuration).

2. The setting (transition to logic 1) of CONF_DONE.

In general, could CONF_DONE be asserted at the same time NSTATUS is cleared for a condition where the very last byte of data transferred to the Arria II GX FPGA contained an error?

Regards,

Nick