Altera_Forum
Honored Contributor
Honored ContributorRegister initialization
Hello folks,
I have a shift register with no resets that I need to initialize. Will an initial value synthesize for Stratix III? Thanks, -BradForum Discussion
9 Replies
Altera_ForumAll registers power up on zero if you set "power up don't care" to false.
In recent compilers they power up to initial value that you set when declaring signals. You will get warning if any register powers up high. You can power up to 'X' to give freedom to fitter.- Altera_Forum
Put a reset signal and assign a value to it when reset = 0
- Altera_Forum--- Quote Start --- I have a shift register with no resets that I need to initialize. Will an initial value synthesize for Stratix III? --- Quote End --- Yes. In practice, all registers in the FPGA initialize to '0' and the software insert's NOT operations to make it look like it initialzied to '1'.
- Altera_Forum
You can now also use an initial statement in your source code to initialize the registers.
- Altera_Forum
initial is for simulation only , it will get ignored during synthesis and will not initialize. quartus 2 has an option in the Assignment editor called Power Up Level. you set it's value either 0 or 1. by default quartus initializes all registers to 0. link your register to that assignment, and set the value for it, to initialize a flip flop or a register to 1 when the system starts up.
- Altera_Forum--- Quote Start --- initial is for simulation only , it will get ignored during synthesis and will not initialize. quartus 2 has an option in the Assignment editor called Power Up Level. you set it's value either 0 or 1. by default quartus initializes all registers to 0. link your register to that assignment, and set the value for it, to initialize a flip flop or a register to 1 when the system starts up. --- Quote End --- This is untrue. Quartus now take initialisation values in code (aswell as async reset values) as the power up value. It has been doing this for several years!
- Altera_Forum
really? for example if i say
module Trickytriestotrickme (slowestclock,WillMyLedLightUp) input slowestclock; output WillMyLedLightUp; reg WillMyLedLightUp; initial WillMyLedLightUp <= 1'b1; always @(posedge slowestclock) begin WillMyLedLightUp <= ~WillMyLedLightUp; end endmodule if i plug led to the altera's pin, will it start from "1" in the real world? - Altera_Forum
Examples taken directly from the Altera HDL Coding Guidelins about register inital values.
http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf example 14–37. verilog register with high power-up value
example 14–38. vhdl register with high power-up levelreg q = 1’b1; //q has a default value of ‘1’ always @ (posedge clk) begin q <= d; endSIGNAL q : STD_LOGIC := '1'; -- q has a default value of '1' PROCESS (clk, reset) BEGIN IF (rising_edge(clk)) THEN q <= d; END IF; END PROCESS; - Altera_Forum
auch....! thats what happens when you study from books written in 1998 :) thank you so much.
