register assignment don't get the wanted delay

i design a one clock delay module with register,when i add it to the top entity,,i don't get the wanted delay in modelsim simulink . but when i simulink the module alone,it is right and get one clock delay module.why? who can help cc2_

in

module ram_control(clk,reset,enable,d_in,c_in,wraddress,wren,rdaddress,rden,enable1,d,c);

input clk;

input reset;

input enable;

input[11:0] d_in;

input[11:0] c_in;

output[11:0] c;

output[11:0] d;

//input[11:0] datain;

output [10:0] rdaddress;

output rden;

output [10:0] wraddress;

output wren;

output enable1;

reg enable1;

reg[10:0] rdaddress,wraddress;

reg rden,wren;

//output [11:0] q_delay;

/*data_RAM i1(

.clock(clk),

.data(datain),

.enable(enable),

.rdaddress(rdaddress),

.rden(rden),

.wraddress(wraddress),

.wren(wren),

.q(q_delay);

*/

reg[10:0] n;

reg[1:0] state;

always@(posedge clk or posedge reset)

//begin

begin

if(reset)

begin

n<=11'b00000000000;

enable1<=1'b0;

state<=2'b00;

rden<=1'b0;

wren<=1'b0;

state<=2'b00;

wraddress<=11'b00000000000;

rdaddress<=11'b00000000000;

end

else if(enable)

begin

if(n<11'd2047)

begin

wren<=1'b1;

if(wren)

begin

n<=n+11'b00000000001;

wraddress<=wraddress+11'b00000000001;

end

else

begin

n<=11'b00000000000;

wraddress<=11'b00000000000;

rdaddress<=11'b00000000000;

end

end

else if(n==11'd2047)

begin

enable1<=1'b1;

case(state)

2'b00:

begin

wren<=1'b1;

rden<=1'b1;

wraddress<=11'b00000000000;

rdaddress<=11'b00000000000;

state<=2'b10;

end

/* 2'b01:begin

if(wraddress<=11'd2047)begin

wraddress<=wraddress+11'b00000000001;

end

else wraddress<=11'd0;

end*/

2'b10:

begin

if(wraddress<11'd2047&&rdaddress<11'd2047)

begin

rdaddress<=rdaddress+11'b00000000001;

wraddress<=wraddress+11'b00000000001;

end

else

begin

state<=2'b00;

end

// state<=2'b10;

//rden<=1'b1;

// wraddress<=11'b00000000000;

end

endcase

end

end

end

reg[11:0] dd_in,cc_in,cc2_in;

always@(posedge clk or posedge reset)

begin

if(reset)

begin

// t<=1'b0;

dd_in<=12'd0;

cc_in<=12'd0;

end

else if(enable)

begin

dd_in<=(~d_in)+12'b000000000001;

cc_in<=c_in;

cc2_in<=cc_in;

end

end

assign d=dd_in;

assign c=cc_in;

endmodule