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Altera_Forum's avatar
Altera_Forum
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14 years ago

regarding verbosity_package.sv errors

in this thread, i see someone else has hit this same problem:

www altera com/forum/showpost.php?p=122019&postcount=10

i can't post that as a link since i only have 1 post...

the response to that question seems more focused on modelsim. however, i am seeing that exact error in quartus when i try to analyze and elaborate in preparation for simulation.

i do not see this problem if i run the simulation in ncsim, so it does seem to be a bug in quartus. i do have sytemVerilog checked everywhere in quartus.

i did a little hacking on this and it really does seem that quartus is confusing a void function for a task. if i edit verbosity_package.sv to make print() return a string and assign the return value of print to a dummy string, the file compiles just fine.

any ideas?

thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    any ideas?

    --- Quote End ---

    Can you post a simple synthesizeable design showing the issue, and perhaps a testbench. I can run the code through Modelsim-SE to see if it complains. That would at least isolate the issue to being with Quartus. You could then file an SR and upload the same design.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    sure, i can do that, i just have to go in and create a brand new one to make sure i don't have any proprietary IP in there. might take me a couple days at the rate things are going.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    might take me a couple days at the rate things are going.

    --- Quote End ---

    Ok, I'll keep an eye out for it.

    Cheers,

    Dave