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Altera_Forum's avatar
Altera_Forum
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9 years ago

Reg: Max5 CPLD 5M160ZE64 clk/gpio pins ...

hi,

i had a question regarding the max5 5m160z cpld.

i need to provide 4 or 5 clocks into my design. the max5 cpld databook says there are only 4 dedicated global clk pins (which can also be used as general purpose IO).

since I need to give more clock inputs into my design compared to the no. of gclk pins available, i wanted to know if it's possible to use other general purpose IO pins to feed a clock into my design?

my design is low speed (about 40MHz). also, i did try to compile my design in QuartusII and assigned the clocks in my design to a general purpose IO (instead of dedicated clock pins) and the tool did not complain.

so i just wanted to know if this (feeding clock into cpld via GPIO) has been tried by someone on actual hardware and/of if there were any issues?

please let me know ...

thanks,

z.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Generally there are other Global signal routes so another clock should be without problem at these frequency..

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    hi,

    thanks for your reply.

    i did look at the max5 cpld datasheet and the input clock rates for standard IOs is something like -

    IO standard family speed

    3.3V LVTTL 5M160Z (C4, C5, I5) 304MHz

    since i am most interested in the 5M160ZE64A5 family, which is not mentioned in the datasheet, is there any information about this particular family's IOs and where could I find it?

    thanks,

    z.