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Hi,
Okay, If you are facing the same issue compare with reference design OR the pin connection guidelines in below links.
http://www.alterawiki.com/wiki/arria_10_transceiver_phy_design_examples https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/arria-10/pcg-01017.pdf Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Best Regards,
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
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I fixed my issue by specifically using a QSFP reference clock. I guess it is intended for driving the transceiver PLL as it is located in the correct place. Your links, however, seem very helpful for other parts of my project. Thanks for linking them. I consider the problem solved now, Thanks.
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