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New ContributorREFCLK PB on a 10CX105YF672E6G
Hello
I have two identical boards integrated with two similar Cyclone 10 GX but having two different speed grades: one with a 10CX105YF672E5G, the other with a 10CX105YF672E5G. On the ...E5G every thing is nominal, but on the E6G, the REFCLK pins seem to be inactive. I have tested this on two ...E6G board ans obtained the same issue. My debug setup is as follow:
- REFCLK clock frequency: 100 MHz
- REFCLK: PIN_N22 (Bank 1D)
- REFCLK signal: LVDS
- REFCLK directly routed on Pin_A3 (Bank 2L)
I also debug the same setup with the the REFCLK: PIN_R22 (Bank 1C) and obtained the same issue.
When I connect my 100 MHz clock on a standard LVDS input routed on the same PIN_A3, it works.
Have similar anomalies already been reported on these Cyclone ...E6Gs?
Best regards
Etienne
3 Replies
WZ2Frequent Contributor
Hi there,
May I ask if you could try using this pin as the input to the IOPLL? If it is used as the PLL input, is the lock signal able to assert successfully? So far, I haven't seen this issue on this specific device.
Additionally, could you please confirm the I/O standard of the input clock signal? Is it AC-coupled?
Best regards,
WZ
ESamaHello
Thank you for your reply.
This pin is used as the input to a IOPLL and the lock signal doesn't assert with the E6G version (and assert with the E5G...)
Configuration of the pin :
- I/O Standard: LVDS
- Input Termination : differential
- AC coupled on the board
Best regards
Etienne
Farabi_AlteraRegular Contributor
Transfer this case back to community as no reply.
regards
Farabi
