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Altera_Forum
Honored Contributor
Honored ContributorRecovery timing violation
Hi all, I have a design with major recovery timing violation (among others). The design wasn't written by me, I'm only editing it, so I'm not fully aware of everything inside it. Th...
Altera_ForumHonored Contributor
Honored ContributorThank you for your responses.
It seems that my issue was this: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01032012_191.html That's why I had large timing violations in the ddr3 emif interface.
