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Altera_Forum
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17 years ago

Recovery Removal and multiclock IP

I'm using ASI receiver IP that works with a lot of clock (135MHz, 337.5Mhz and 337.5Mhz shifted of 90°). All theese clock are done by the same PLL that is fed by a 27Mhz (that is the natural clock...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

In the sdc file i have two constraints commented out : 


# set_false_path -from  -to 
# set_false_path -from  -to

These can be used to break the reset paths between certain clock domains. With your change, if you used : 


set_false_path -from  -to

You might be able to cut the paths you need. Note that you have to be very cautious when using general constraints like these because it might cut more than you need.

Hope that helps, let me know if it doesn't solve your problem.

**I made that changes you described and compiled in 9.0sp2. Without the new constraint it had recovery failures on the rd_clk domain from wr_rstn to many different paths. With the constraint in there it had no failures.

edited for : spelling errors...