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Altera_Forum
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16 years ago

Recovery Removal and multiclock IP

I'm using ASI receiver IP that works with a lot of clock (135MHz, 337.5Mhz and 337.5Mhz shifted of 90°). All theese clock are done by the same PLL that is fed by a 27Mhz (that is the natural clock...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Actually ignore what i said in the previous post. I spoke too early. It is still true of the DDR2HP core, but what i talked about with the DCFIFO cores does not appear to be true as of yet.

I looked into dcfifo.tdf and saw where it used the aclr signals, but what i was looking at was not the general use functions but some specific implementations when not using EAB blocks i believe. After further investigation it looks to call some function to generate the fifo files, and it passes the arst signal into that function. I haven't dug deeper, but it looks to be a little more complicated that i first believed. I'll update here if i have any new breakthroughs with the DCFIFO.

Time to wipe the egg off my face,

Kevin