Reciprocal Counter

Currently the trigger is synchronous with the clock since its being generated in the FPGA as a divider. It is one clock cycle wide (i.e with a 100Mhz clock - 99,999,999 cycles off, 1 cycle on to have a rising edge once every second). The beauty of the reciprocal counter is that your trigger doesn't have to be very accurate, it being off by a few us is unimportant. It might be offloaded to an atomic clock as an exercise in pedantry, but thats far off in the future.

The thing is, when I use a synchronously generated input signal - i.e. a divider in the fpga. Then the reading I get from the counter is exactly correct (and my fancy $10K professional counter agrees with it). When I migrate to an external signal source, it begins to act wacky even though the clock domains are supposed to be synchronized since I'm using the Oven clock out from the signal source as my external clock source.

If it matters, the frequency I'm trying to measure is ~420Khz.

edit: Could the problem be that since it is synchronous with the clock then the dual condition (posedge clock or posedge trigger) be causing the circuit to trigger twice in quick succession? i,e, the asynch clear is propogating through the registers while the clock is making the registers increment?