Reciprocal Counter

What is the nature of the trigger signal? It appears to be asynchronous to the clock. What is it's expected duration?

You at least need to resynchronize "trigger" to your clock domain before you attempt to make use of it. You are using it as an asynchronous clear or set to 66 flip-flops. you have no way to guarantee that they all take the action at the same time (due to routing delays, variations in the fabric, etc.). You need to make a "safe" copy of the trigger signal in your clock domain.

something like this maybe:

reg    trigger_r;
wire        trigger_edge;
assign trigger_edge = trigger_r & ~trigger_r;
always @(posedge clock)
     trigger_r <= {trigger_r,trigger};

Then use "trigger_edge" as a synchronous input to your logic and do not use "trigger". This of course implies a few things:

1 - You're okay with some latency on trigger.

2 - trigger is at least two clock periods in duration.

If neither of these is acceptable, there are more fancy methods that you can use to latch trigger into the clock domain. Specifically, you'll have to asynchronously latch trigger and synchronously clear it.

Jake