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Altera_Forum's avatar
Altera_Forum
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16 years ago

Real worth & Simulation has big mismatch.

Hey again kind folks of Alteraland,

The design I'm working on has a timing simulation delay of 10ns. However, when it's implemented, the pins of the FPGA is producing an output that has a delay of 6 microseconds. What is a good process of debugging this problem? I have no experience of debugging this problem as I can't hook up a probe in the FPGA chip.

Thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    There is no hardware in a FPGA, that could produce a microsecond range delay on its own, except for a huge capacitive pin load, or a moderate load with an open drain output. You may want to describe your test setup more detailed.