Forum Discussion
Seadog
Occasional Contributor
Occasional ContributorRead pipelining in AXI-4 interfaces
This question is in regards to AXI-4 slave interfaces, in particular the AXI-4 interface on the HBM2 memory controller (S10 MX devices).
AXI-4 specifically supports out-of-order responses to read ...
AdzimZM_Altera
Regular Contributor
Regular ContributorAs has been mentioned from sstrell, out of order transaction is not supported.
You can refer to Embedded Peripherals IP User Guide in the link below: https://www.intel.com/content/www/us/en/docs/programmable/683130/22-1/axi-4-interface.html
