Altera_Forum
Honored Contributor
Honored ContributorRead from onchip memory
Hi ,
please i need to know if it is possible to read from onchip memory through VHDL. Other way, there are a vhdl instruction to read from onchip memory through VHDL?:(Forum Discussion
5 Replies
Altera_ForumExport interface pins from QSYS and control it as You like.
- Altera_Forum--- Quote Start --- Export interface pins from QSYS and control it as You like. --- Quote End --- Thank you for your reply, Please can you more clarify how can i do this action under SOPC builer.
- Altera_Forum
In SOPC builder You'd need to create a new SOPC component to interface it with the memory. It'd have memory master and conduit interfaces connected. I am not sure, but check for cores in MegaWizard. Maybe You'll find something already done.
- Altera_Forum
TO_BE_DONE
- Altera_Forum--- Quote Start --- Hi Aflatoun, You can easily do it with the Component Editor. Just add one master interface. Then on the signal tab add the signals you want to export and assign them to the avalon master interface signals. Component editor will then create a custom component whose tcl file is similar to this:
If you prefer you can directly create a _hw.tcl file with this content and copy it in the <Altera>\<version>\ip\user_components directory. The new component will appear in the Bridges and Adapters/Memory Mapped section of SOPC builder. --- Quote End --- Oh Cris72 thank you very much for this. i will try to implement it and inform you if it work fine.# +-----------------------------------# | module ext_master_interface# | set_module_property NAME ext_interface set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property GROUP "Bridges and Adapters/Memory Mapped" set_module_property DISPLAY_NAME ext_master_interface set_module_property INSTANTIATE_IN_SYSTEM_MODULE false set_module_property EDITABLE true# | # +----------------------------------- # +-----------------------------------# | files# | # | # +----------------------------------- # +-----------------------------------# | parameters# | # | # +----------------------------------- # +-----------------------------------# | connection point avalon_master# | add_interface avalon_master avalon start set_interface_property avalon_master adaptsTo "" set_interface_property avalon_master burstOnBurstBoundariesOnly false set_interface_property avalon_master doStreamReads false set_interface_property avalon_master doStreamWrites false set_interface_property avalon_master linewrapBursts false set_interface_property avalon_master ASSOCIATED_CLOCK clock set_interface_property avalon_master ENABLED true add_interface_port avalon_master ext_address address Output 16 add_interface_port avalon_master ext_cs_n chipselect_n Output 1 add_interface_port avalon_master ext_wr write Output 1 add_interface_port avalon_master ext_rd read Output 1 add_interface_port avalon_master ext_writedata writedata Output 32 add_interface_port avalon_master ext_readdata readdata Input 32 add_interface_port avalon_master ext_be byteenable Output 4 add_interface_port avalon_master ext_wait_n waitrequest_n Input 1# | # +----------------------------------- # +-----------------------------------# | connection point clock# | add_interface clock clock end set_interface_property clock ptfSchematicName "" set_interface_property clock ENABLED true add_interface_port clock clock clk Input 1 add_interface_port clock reset reset Input 1# | # +-----------------------------------
