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Yassine-Ca's avatar
Yassine-Ca
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1 year ago

Read from memory

Hello, I'm working on DE1-SoC Cyclone V FPGA. I have prgrammed the FPGA to store a static data to the onchip memory created on Platform Designer, this generated the definitio...
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RichardT_altera's avatar
RichardT_altera
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1 year ago

The best way is to go through the application note and run successfully using the design example.

Alternatively, you can go through the steps using your design and verify the signal integrity/clock toggling of the JTAG chain in step 3.


Application Note:

https://www.intel.com/content/www/us/en/docs/programmable/826921/24-3/about-this-application-note.html

Arria 10 example design:

https://www.intel.com/content/www/us/en/design-example/842175/arria-10-system-console-getting-started-design.html


Regards,

Richard Tan