Forum Discussion
Yassine-Ca
New Contributor
New ContributorRead from memory
Hello, I'm working on DE1-SoC Cyclone V FPGA. I have prgrammed the FPGA to store a static data to the onchip memory created on Platform Designer, this generated the definitio...
RichardT_altera
Super Contributor
Super ContributorThe best way is to go through the application note and run successfully using the design example.
Alternatively, you can go through the steps using your design and verify the signal integrity/clock toggling of the JTAG chain in step 3.
Application Note:
Arria 10 example design:
Regards,
Richard Tan
