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Altera_Forum's avatar
Altera_Forum
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16 years ago

Read from file in vhdl

Hi,

I have a whole heap of bits I need to hard-code into my hardware. Instead of writing them directly into my vhdl code I was wanting to be able to load them into the code via a .dat file or something similar. I have tried to do this using the readline and read statements (using the textio package) in Quartus but it doesn't seem to work.

Firstly, I get an error saying that Quartus doesn't know what the "std_logic_textio" package is (it says the IEEE library doesn't contain it). When I remove this line from the code, I get an error saying that "read is not a subprogram, a type, or an array object" (it does however understand the readline command). I'm thinking that this is probably because I had to remove the package I mentioned above.

I've been looking on the web to see if there is any way to fix this, but it seems that this stuff cannot be synthesised and is usually used in testbench designs, so Quartus doesn't like it. I'm wondering, firstly, If I have done something wrong here, or is there any other way to read data from a file into a synthesisable vhdl file.

Thanks in advance for your help.:)

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Usually, constant data are read in at compile time from a *.hex or *.mif file to a ROM. *.hex has the advantage of working both in simulation and synthesis.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    2 problems.

    1. VHDL can only read text files (you can work around it to read in data files, but behaviour is not consistant from tool to tool). textio is really just a subset of std.textio that allows you to read/write directly to/from std_logic_vector. The main functions are in std.textio. Std_logic_textio is also a synopsis package and not an IEEE standard, which is probably why quartus just doesnt have that package anyway.

    2. You cannot use textio in quartus for synthesis. Its a real pain because Xilinx allows it. The only way to do it is via direct instantiations of altsyncrams that allow you to specify a .mif or .hex as the initialisation file.