Read from file in vhdl

2 problems.

1. VHDL can only read text files (you can work around it to read in data files, but behaviour is not consistant from tool to tool). textio is really just a subset of std.textio that allows you to read/write directly to/from std_logic_vector. The main functions are in std.textio. Std_logic_textio is also a synopsis package and not an IEEE standard, which is probably why quartus just doesnt have that package anyway.

2. You cannot use textio in quartus for synthesis. Its a real pain because Xilinx allows it. The only way to do it is via direct instantiations of altsyncrams that allow you to specify a .mif or .hex as the initialisation file.