Read-during-write "don't care" behavior for on-chip memory

For Cyclone IV (M9K), it is stated quite clearly in the documentation (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51003.pdf) that don't care means either old value or new value, and not a combination of both or a metastable signal:

"For mixed-port read-during-write operation with dual clocks, the relationship

between the clocks determines the output behavior of the memory. If you use the

same clock for the two clocks, the output is the old data from the address location.

However, if you use different clocks, the output is unknown during the mixed-port

read-during-write operation. This unknown value may be the old or new data at the

address location, depending on whether the read happens before or after the write."

The Xilinx 7 series memory user guide (http://www.xilinx.com/support/documentation/user_guides/ug473_7series_memory_resources.pdf) appearently states that for dual-clock memories, RDW is never safe regardless of the mode, and for single-clock, RDW is safe if the write port is in READ_FIRST ("old data") mode, but not in WRITE_FIRST ("new data") mode.

I'm starting to think that it would be a good rule to always avoid read during write unless absolutely necessary.