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Which template are you referring to? In VHDL simulation you can guarantee old data or new data for the read value by either using a signal as the ram storage (old data) or a shared variable (new data). You cannot get an X. X would only be possible if you added extra code to explicitly return X (because otherwise you get a multiple driver situation). The altsyncram will have this in it.
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Open a file in Quartus and go to Edit -> Insert Template -> VHDL -> Full Designs -> True Dual-Port RAM (single clock). Have a look at the comment in the top of the template. Funny enough, this template will give you "new data" behavior for write A/read B and "old data" for write B/read A. At least with my simulator, with a different simulator executing the processes in the opposite order you will get the opposite. The hardware will be "don't care", whatever that means.
I have always assumed that you either got "old data" or "new data", but now I don't know what to believe.
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