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In the real chip, The only 2 options are old data and new data. If new data is chosen, then extra logic is required to pass the new value through to the read port.
The whole point of dont care is you let the synth tool decide which version of ram to build.
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I think you are not right Tricky. Here is a cut from an Altera internal memory doc:
The same-port RDW occurs when the input and output of the same port access thesame address location with the same clock.
The same-port RDW has the following output choices:
■ New Data—New data is available on the rising edge of the same clock cycle onwhich it was written.
■ Old Data—The RAM outputs reflect the old data at that address before the writeoperation proceeds.1 Old Data is not supported for M10K and M20K memory blocks insingle-port RAM and true dual-port RAM.
■ Don't Care—The RAM outputs “don't care” values for the RDW operation
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