Read-during-write "don't care" behavior for on-chip memory

In the real chip, The only 2 options are old data and new data. If new data is chosen, then extra logic is required to pass the new value through to the read port.

The whole point of dont care is you let the synth tool decide which version of ram to build.

Which template are you referring to? In VHDL simulation you can guarantee old data or new data for the read value by either using a signal as the ram storage (old data) or a shared variable (new data). You cannot get an X. X would only be possible if you added extra code to explicitly return X (because otherwise you get a multiple driver situation). The altsyncram will have this in it.

So, I think you need to be a little clearer about exactly what you're using. The whole point of return 'X' is for people who do care - to ensure they never read and write to te same port on the same clock cycle.