--- Quote Start ---
When instantiating dual-port RAMs (e.g., M20K/M9K/MLAB), Altera documentation defines three different read-during-write behaviors, "old data", "new data" and "don't care". Apparently "don't care" is what you get when inferring true dual-port RAMs using the Altera VHDL template, since whether you get the old data or new data will be undefined in simulation. (It depends on the order the simulator executes the two processes. This is also pretty bad since you easily end up with mismatches between simulation and hardware. In any case it is definitely much safer to use the altsyncram macro.)
What exactly does "don't care" mean in this context? For my application I don't care whether I get the new or old value when reading and writing to the same address in the same clock cycle, but anything else could have bad consequences.
- Is there any chance I could get a mix of the old and new value? (i.e., garbage?)
- Is there any chance I could get a meta-stable output?
While I have a single-clock true dual-port RAM in M20K (I need one write port and two read ports), the question apparently applies to all RAM configurations, including dual-clock RAMs and even single-port RAMs. (The Arria 10 handbook says under the "don't care" mode that "For M20K memory, the Quartus Prime software does notanalyze the timing between write and read operations.")
--- Quote End ---
My guess is that "don't care" option is useful in case your design actually avoids read during write. You shouldn't otherwise use it but select old data or new data as available.
Honored Contributor
