Forum Discussion
tedh4ddv
Occasional Contributor
Occasional ContributorRemote Update for Cyclone 10 LP - CSR
Using Platform Designer, we've combined three IP Cores in a Cyclone 10 LP project to accomplish three functions: 1) allow an external processor access to the FPGA via a SPI bus 2) write a .jic file...
tedh4ddvOccasional Contributor
Occasional ContributorI am using a 20MHz clock. Generated from a PLL within the FPGA.
