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Occasional Contributor
@Luckyguide wrote:Thanks for your response,
The signals are not terminated, and I don't have a good reference signal to compare to. I tried making a reference with a lower frequency of 3KHz but that also showed the same problem with voltage overshoot.
The current is what i specified in the pin planner, I didn't measure it during the test.
I'm not quite sure about the protection diodes, as I couldn't find any information about it anywhere. The trace is 10cm if you're referring to the cable length of the GPIO to the oscilloscope probe.
The MAX 10 does not have an internal source resistance capability and I would prefer to not make any circuit changes, as I am wondering why the direct output at the GPIO is not a 50% duty cycle 3.3V PWM signal. Isn't it that this constant overshooting will damage the GPIO of the development board over time if I don't fix the overshoot at the GPIO?
I am aware that I can add capacitors and resistors to stop the overshoot, but I am rather concerned about the behaviour of the development board and I feel like either I have done something wrong in pin planning or I am missing something.
So the overall device current.
That trace is very long. Simple transmission line theory suggests with an o/c destination the trace will go to 2 x VCC or in your case the voltage is probably limited by protection diodes ~5V. Therefore I might expect to see a nominal 2.5V average.
Can you change the drive current, or the slew rate? I would set these to be the lowest and slowest.
I know you don't want to change the PCB, but you should think transmission line and termination for all signals, especially when driven with sub-ns rise and fall times. 10cm represents a time of ~0.5ns. I hope there is just one destination pin?
A series termination at the source would be best, the alternative is a parallel termination at the destination.
The overriding consideration is does the system work as intended?
New ContributorOccasional Contributor
@Luckyguide wrote:
I can try to lower the amps,
I don't believe the current is particularly relevant.
@Luckyguide wrote:
but I can’t change the slew rate.
Yes, there is only 1 destination pin.
Ok
@Luckyguide wrote:
I hope my question can be answered as to how the output voltage can even reach 4.7V if I only send a 1 or a 0 from my program. Theoretically it should then only be 0-3.3V maximum with perhaps a little overshoot?
I have already answered this. If an unterminated transmission line is driven, then the reflected voltage will return and add to the source drive voltage. I recommend you look up about this. An example article:
Super ContributorHi,
do you know trace transmission line impedance? Depends on width and layer stackup, you can e.g. use popular Saturn PCB toolkit for calculation.
MAX10 LVTTL33 4mA IO standard has about 60 ohm typical output impedance, not far from lower range of expextable trace impedance. In any case you don't get much overshoot at the driving pin but larger overshoot at open trace end. Where do you measure the shown waveform?
I'm not sure if measured 4.7 V is real, it might be also caused by unsuitable probing. It's no easy to measure correct waveforms of fast FPGA output signals with passive probes.
I calculate maximal overshoot magnitude of 4.125 V at open trace end for 60 ohm pin impedance and 100 ohm trace ( 3.3*2*100/(60+100) ), but trace impedance is most likely lower.
