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New Contributor

1 year ago

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Difficulty using clocks on F-Series Development Kit

I am having a difficult time understanding how to use the clock on the Intel Agilex 7 FPGA F-Series Development Kit (P-Tile and E-Tile) DK-DEV-AGF014EA. I tried creating a simple design to toggle the...

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roeekalinsky
1 year ago
Hi @JackLusenhop ,
Not sure what aspect specifically is giving you trouble, but here's a simple example design that toggles an LED using the 100 MHz clock on the DK-DEV-AGF014EA board. See attached.
-Roee
example.zip3 KB

sstrell

Super Contributor

1 year ago

I'm not familiar with the IP you mention. Do you mean a clock control block (altclkctrl)? These are used for selecting clock sources, global clock enables, and connections to the global clock routing channels of the device (the global I believe you are asking about).

Always a good idea to go through the user guide for your device: https://www.intel.com/content/www/us/en/docs/programmable/683761/24-1/fpga-clocking-and-pll-overview.html

JackLusenhop

New Contributor

1 year ago

Hi @sstrell,

Thanks for the link, I was able to use the IOPLL IP in the guide as a fix to the issue as well. I wonder why instantiating the IOPLL IP had the same affect for me as setting the IO Standard. I will have to look more into it. Anyway, thanks for the help!

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Difficulty using clocks on F-Series Development Kit

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