Forum Discussion
Occasional ContributorAvalon to AXI implementation
Super ContributorHi @MichaelB
From what I found, the DDR4 EMIF core & Avalon MM Clock Crossing Bridges does not seem to support maximum pending write transactions. The interface must have both response and writeresponsevalid signals which these IP does not have. You may create a custom component though by adding the respective signals. fyi, the maximum pending read transactions need readdatavalid signal.
Will the interconnect resolve data width conversion and align the bursts?
Make sure there is no error in the system message and the platform designer should take care most of the interconnect between the interface.
You may check the chapter 5.1. Memory-Mapped Interfaces for further details:
If you have further question on EMIF, I would recommend you to open a new forum case on EMIF related questions. As I am not an expert in EMIF unfortunately.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
Occasional ContributorHi Richard,
yes, I recognised this, too, that here are some signals missing (EMIF core & Avalon CCB).
- Is there an option in the Avalon CCB & EMIF core to enable those?
- How can I create a custom component for an standard IP? Would this be a custom component instantiating the EMIF core?
I tried to edit the interface of those IP cores in the component section in QSYS but I cannot add further signals.
I already read through the EMIF user guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-emi.pdf) but I could not found any setting to enable/disable pending write transactions.
Currently I am using the autogenerated interconnect from QSYS to resolve 256b AXI (BL = 16) to 512b Avalon (BL = 8).
Here I did not see any errors in the QSYS only the hint that an Avalon adapter will be inserted between AXI <-> Avalon.
Are there any special settings of the mm_interconnect I have to configure to do the bus conversion?
From the documentation of the Platform Designer I assumed this will be done by mm_interconnect automatically.
Do you have any reference design (QSYS) where a AXI <-> Avalon connection with bitwidth conversion + burst conversion is done?
That would be helpful to understand the settings on both sides to align them for the best throughput performance.
Kind regards,
Michael
- RichardT_altera
Hi @MichaelB
Is there an option in the Avalon CCB & EMIF core to enable those?
Unfortunately I do not see a way to enable those.
How can I create a custom component for an standard IP? Would this be a custom component instantiating the EMIF core?
You may launch the Component Editor by double-clicking New Component at the top of the IP Catalog or by selecting New Component from the File menu.
You may checkout the training video below. Chapter 9. Creating custom component.
https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsys3000.html
Are there any special settings of the mm_interconnect I have to configure to do the bus conversion?
You do not need to configure anything. As you mentioned, this will be done by mm_interconnect automatically.
https://www.youtube.com/watch?v=LdD2B1x-5vo
Do you have any reference design (QSYS) where a AXI <-> Avalon connection with bitwidth conversion + burst conversion is done?
This is the closest design example that I found with AXI and Avalon connection.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.- RichardT_altera
Hi @MichaelB
May I know does my latest reply helps?
Do you need further help regarding to this case?
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
