Thank you, here's my update:
In my design, a RapidIO II IP Core in A10 GX FPGA is used, trying to establish link with another chip(link partner).
The SRIO of link partner is composed of Mobiveil GRIO IP Core and SiliconCreation SerDes IP Core.
In 1x mode, link training is successful, and MAINTENANCE/SWRITE/DOORBELL transactions are verified.
In 4x mode, link training is failed. For FPGA, rx_is_lockedtodata=4'hF, four_lanes_aligned=1, two_lanes_aligned=1, port_initialized=1, link_initialized=0. For link partner, lane_sync[3:0]=4'hF, both four_lanes_aligned and two_lanes_aligned toggle between 0 and 1, port_initialized=0, link_initialized=0.
That means, in 4x mode, link partener cannot be aligned steadily. According to RapidIO Specification v2.2 part6 chapter 4.12.4.3, if all four lanes recept /A/, a ||A|| is counted, and 4 consecutive ||A||s after lane_sync[3:0]=4'hF will result four_lanes_aligned=1. And the alignment state machine will detect a misaligned column, which will cause the lane alignment state machine goes to NOT_ALIGNED state.
Since the alignment of link partner is unstable, I'm trying to figure out why its four_lanes_aligned toggles. First I want to know that, whether the /A/s sent by FPGA's four lanes are fully synchronous or not, how can I verify that? After port_initialized=1 but link_initialized=0, does FPGA still transmit /A/ in idle sequence?
Regards.
Occasional Contributor
