Random results on FPGA

that was the root cause of the issue.

adding this uncertainty of 500 ps in my sdc solves the unpredictable results.

set_clock_uncertainty -add -from [get_clocks *] -to [get_clocks *] -setup 0.5

set_clock_uncertainty -add -from [get_clocks *] -to [get_clocks *] -hold 0.5

"Clock uncertainty" is the interval of confidence around the ideal clock

value, such that the measured value is always within the stated interval.

Common sources of clock uncertainty include clock jitter, duty cycle

distortion, and phase shift error. Due to these sources, clock uncertainty

must be factored in to guard against deep submicron effects that are not

explicitly reflected in the timing models.

PLL phase error, PLL jitter, I/O buffer, clock network noise, core noise,

On chip variation (die process, temperature), crosstalk between nets.

Wich is specially true for my complex design with more thqn 100 clocks and plenty of clock gating.