Altera_Forum
Honored Contributor
15 years agoQuick JTAG FPGA reconfiguration
Hello
I want to reconfigure my FPGA as quick as possible using a host pc running linux and jtag (usb-blaster) as programming interface. If I run the programmer "quartus_pgm" it takes a long time from hitting enter until the FPGA is reconfigured. Find the log at the bottom. It is not only about the real reconfiguration, it also takes quite a while from hitting enter to reconfiguration starts (~10s). I assume the programmer does some checks on the sof file in order to make sure it is a valid configuration file. However, since I'm interested to optimize the time from "the programmer being called" to the "The FPGA is reconfigured and starts working" I wonder if there are any options to speed it up, maybe options to prevent validation checks, etc. I didn't find anything useful in the Quartus manual or in the help of quartus_pgm. Info: ******************************************************************* Info: Running Quartus II Programmer Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version Info: Copyright (C) 1991-2011 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, Altera MegaCore Function License Info: Agreement, or other applicable license agreement, including, Info: without limitation, that your use is for the sole purpose of Info: programming logic devices manufactured by Altera and sold by Info: Altera or its authorized distributors. Please refer to the Info: applicable agreement for further details. Info: Processing started: Wed May 18 18:35:46 2011 Info: Command: quartus_pgm -c usb-blaster -m jtag -o p;led_sof/irp_led3.sof@2;EP 1AGX90 Info: Using programming cable "USB-Blaster [USB 2-1.1]" Info: Using programming file led_sof/irp_led3.sof with checksum 0x00CE89FC for d evice EP1AGX90EF1152@2 Info: Started Programmer operation at Wed May 18 18:35:59 2011 Info: Configuring device index 2 Info: Device 2 contains JTAG ID code 0x021230DD Info: Configuration succeeded -- 1 device(s) configured Info: Successfully performed operation(s) Info: Ended Programmer operation at Wed May 18 18:36:04 2011 Info: Quartus II Programmer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 174 megabytes Info: Processing ended: Wed May 18 18:36:04 2011 Info: Elapsed time: 00:00:18 Info: Total CPU time (on all processors): 00:00:12 Thanks and Regards, Jogges