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Altera_Forum
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11 years ago

questions about the DDR3 memory DQ pins

Hello everyone, I have a question about the Cyclone V SOC. On page 14 of the soc dev kit schematic C5_SOC_DEVKIT_D2.pdf, DQ pins of DDR3 seem all scrambled, like DQ0 of DDR3 is connected to HP...
Altera_Forum's avatar
Altera_Forum
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11 years ago

As long as you keep D[7..0] paired with DQS[0]/DM[0], and D[15..8] paired with DQS[1]/DM[1], etc... you can scramble the data bits in each byte lane any way you want for the reasons Dave explained. Some memory vendors do not even bother to label the individual bits because it doesn't matter if they are scrambled.