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Altera_Forum's avatar
Altera_Forum
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14 years ago

question regards to delay for some basic digital component

Hi All, I am wondering what is the delay for a AND (OR,NOT) gate in latest ASIC technology? and what about a typical flip-flop? The reason I ask is I want to calculate the delay of my digital d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

If you are dealing with fpga then there are no gates as you see in RTL code. Code or schematic is mapped to LUTs/registers and dedicated DSP blocks. It might be best to check timing simulation model to tell you what you want.