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ContributorQuestion on Transceiver's Input Referance Clock should be placed close to Transmit PLL? (UG01143 - Scetion3.2)
Hi there, we use A10 GX-057 device. There is a description on UG-01143 section 3.2, page 380-381, "For betst jitter performance, Intel recommends placing the (Transceiver's) input referance clock as...
- Hi, If you plan a design and it is auto route Quaruts will automatically place,If not make the constrain in Quartus qsf file. So in simple words it FPGA depend . Regards, Rs
