Question about set_input_delay and set_output_delay

For -min 1, I was just making it up, so I can't say it's uncommon or not. It's probably not, but I've seen about everything under the sun. Note that source-synchronous devices can spec "strange" tsu/th requirements, which when you work it out, relate to saying if the clock should be edge-aligned or center-aligned.

Quartus should be increasing the I/O buffer itself. If the requirements are physically impossible to meet, there may be a solution but it gets tricky. For example, if Quartus increases the I/O delay chains, they it increases the output Tco max/min, since the delay chains vary over PVT. By increasing this spread, you basically hurt timing. Another way to do it would be to manually shift the PLL output forward a bit. This pushes out the time the data comes out without increasing the max/min spread, since PLL shifts are PVT invariant. That's where it gets complicated. (And of course, there are scenarios where it just won't close timing, which is where faster speed grades, faster device families, high-speed transceivers, etc. all start to come into play)