Question about set_input_delay and set_output_delay

Always look at your setup and hold relationship first. When you say the set_output_delay -min -4ns, does that mean the TCOmin = 4ns? It depends on the hold relationship. If the clocks are edge aligned(and most likely they are), then the hold relationship is 0ns. With a 0ns hold relationship, and an external delay of -4ns, then the FPGA needs to add at least 4ns of delay to get back to 0. So you're right, but it's important to think about the hold relationship, as you can create cases where it's not 0.

As for programmable I/O delay, depends what you mean. It can dynamically be programmable for interfaces that need to be dynamically adjusted. For example, you could have something that plugs into the FPGA and the I/O relationship is unknown, and the user has to dynamically adjust that and find the correct setting in system. (I've seen this with Flash interfaces where they could come from many vendors, all with different specs)

It's also programmable through the Assignment Editor. This isn't dynamic, just forcing it. Some users prefer doing this over timing assignments. (I've heard Xilinx doesn't adjust their I/O delay chains to meet timing, and the user has to do it, so it may come from that perspective). I've seen users try different settings in the lab and then force the delay chains, regardless of their timing constraints. It's also just a fail-safe in case the fitter makes the wrong choices.

Finally, in your example where the TCOmin is 4ns. That has to be at the Fast Corner to meet that. Let's say it meets that by being 4.5ns. In the Slow Corner, it may be twice that at 9ns, barely meeting the 10ns setup relationship. If there's a max output delay, it may be impossible to meet timing.

Another way I like to look at it is the the setup relationship - hold relationship is the data rate. So for a 10ns clock, with setup of 10 and hold relaitonship of 0ns, we're trying to move data every 10ns. The external delay's max - min is how much margin is chewed up external. So if set_output_delay -max 4ns and -min -1ns, then 4 - (-1) = 5ns, or half the margin is used externally, and the FPGA has a 5ns window to work with. Finally, there is the actual -max and -min values, which show where the FPGA must pass data through. (i.e. a -max 4 and -min -1 is different than a -max 6 -min 1, the FPGA must pass data through 2ns earlier in the second case). Just another way to look at them. Sometimes it makes it more clear, sometimes it's more confusing. :)