Honored Contributor
Honored ContributorThank you so much, Rysc.
You have explained the set_output_delay -max 4.0, and I totally understand it now. Now, I come up with another question following your explanation, but just to the opposite: If I have a 10ns clock, the external device's hold time is 4 ns, ignoring the board delay,then I set set_output_delay -min -4.0, so the FPGA should have its Tcomin = 4ns. In this case, am I constraining the FPGA to add delay to its output(if the original Tco < 4 ns)? If my guess is correct, then: You mentioned "Quartus will modify I/O delay chains to try and meet this timing. ", so if this constraint can make the FPGA adjust its I/O delay automatically, why is the programmable I/O buffer still provided by Altera? Is that an alternative manual way for the user to change the I/O timing? Still using my example above, say the the original Tco =1ns < 4 ns, we need to add at least 3ns to satisfy the 4ns external device hold time requirement. If after applying the constraint, the analyzer reports a negative slack for the hold(which means the Fitter tried to adjust the I/O delay,but failed to provide enough), shall I now insert the I/O buffer? Thank you very much again! --- Quote Start --- Look at the TimeQuest User Guide on alterawiki.com about these constraints. Yes, they do just tell the external delays(aka setup and hold, depending on how you look at it). But you also have a clock period. So if the clock is 10ns, and your set_output_delay -max 4.0, then you're also saying the FPGA needs to get it's data out by 6ns after the clock edge or you'll fail setup at the external device. So you are constraining the FPGA. Quartus will modify I/O delay chains to try and meet this timing. (It will not phase-shift the clock, or promote/demote clock trees). If you just use -max, then -min gets the same value. That is unrealistic though, and it is recommended to use both. --- Quote End ---
