Question about set_input_delay and set_output_delay

Look at the TimeQuest User Guide on alterawiki.com about these constraints.

Yes, they do just tell the external delays(aka setup and hold, depending on how you look at it). But you also have a clock period. So if the clock is 10ns, and your set_output_delay -max 4.0, then you're also saying the FPGA needs to get it's data out by 6ns after the clock edge or you'll fail setup at the external device. So you are constraining the FPGA.

Quartus will modify I/O delay chains to try and meet this timing. (It will not phase-shift the clock, or promote/demote clock trees).

If you just use -max, then -min gets the same value. That is unrealistic though, and it is recommended to use both.