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TA_YO_O's avatar
TA_YO_O
Icon for New Contributor rankNew Contributor
1 year ago

Question about power sequencing on agilex7

Regarding agilex7 FPGA, the document "ug-ag-pwr-683373-666351.pdf" states that the power sequence should be in the order of group 1 to group 3.

For example, what kind of problems would occur if groups 1 to 3 were accidentally powered on at the same time?

Damage to the agilex7 device, increased current consumption, etc.

Due to the board design, groups 1 to 3 will be installed at the same time, but I am considering powering them on in the following order. Will this be a problem?

1. Power on groups 1 to 3 at the same time.

2. After about 500 ms, power off groups 1 to 3.

3. After 1 second, power on groups 1, 2, and 3 in the order of the power sequence.

Power

3 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    you know that 1. and 2. are violating power sequencing requirements. There's apparently no guaranteed behaviour. User guide just states:
    "Design your power supply solution to properly control the complete power sequence. The requirements in this section must be followed to prevent unpredictable current draw to the FPGA device, which can potentially impact the I/O functionality."

    It says unpredictable, which IMHO includes possible damage. How likely - I don't know.

    I see that Cyclone 10 GX handbooks specifies relaxed power down sequencing which can be used under circumstances (if the rails are not actively discharged). It guess that the present user guide tries to specify a clear scheme, leaving out possible exceptions and circumventions.

    This also means, be happy if you didn't yet observe FPGA damage but try to reach the main road in a redesign.

    Regards

    Frank

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi TA_YO_O,


    As per FvM said, violating the power sequencing requirements could potentially damage the FPGA. The user guide mentions that improper sequencing may lead to unpredictable current draw and I/O issues, which includes the risk of board damage.

    I recommend adjusting the design to follow the specified guidelines to avoid this risk.


    Best regards,

    Fakhrul


  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.