Question about Monitor

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I am talking about the outputs. The pcie_core_clock and pcie_core_reset are the outputs form the PCIe IP core.

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Are they outputs from the 'root complex' (your BFM design) or from the 'end-point device' (your FPGA design).

The reference clock from the root complex might be required by the end-point device if the two are to be synchronous ... or that same connection could be via a common clock in your testbench. I would look at Altera's examples to see what they do.

This webcast implies that Altera's examples have a PCIe BFM

http://www.altera.com/education/webcasts/all/source-files/wc-2011-pcie-technology-design-fpga/player.html

Earlier you implied that Altera did not.

Setting up the testbench I have described is a good exercise in learning the tools. Once you've got it working, you should go back and check out the newest Altera PCIe examples ... perhaps they have improved.

Cheers,

Dave