Question about Monitor

Hi Aditya,

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... These systems have no bus ... I am not using any Bus [such as PCIe/ixp bus] and the connection is through the Avalon switch fabric.

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The Avalon switched fabric is a bus protocol. The Altera Verification IP Suite contains BFMs for testing the protocol(s).

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... when I include the bus [I am using a simple expansion bus [ixp]] ...

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What is IXP? Is it the old ARM XScale bus?

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... when I connect the master of the bus to the slave of the RAM ...

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If you have an external processor connected to an Avalon fabric, then the interface should be an IXP-to-Avalon bridge. If the external bus can only be owned by the processor, then the bridge will only have an Avalon-MM master interface on the Avalon side. If however the external bus can be arbitrated for by the processor or the FPGA, then the Avalon interface can have both master and slave interfaces.

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... here are the difficulties I face ...

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The Altera Verification IP suite Avalon BFMs are for testing Avalon components.

For an IXP-to-Avalon bridge design, you would require both Avalon BFMs and IXP BFMs, and monitors for those buses. The testbench for your bridge design would contain your bridge component, the bus monitors, and the BFMs. Your test case generator would throw lots of transactions at the design in an attempt to test every path through your bridge code (code coverage would tell you what is missed). Illegal activity would trigger assertion violations. Your tests would include transactions where both the IXP master and an Avalon-MM master issued transactions to the RAM and checked the results. This would result in simultaneous accesses that would be arbitrated by the slave-side arbitration inside the FPGA.

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I have tried to explain things as clearly as possible, If I still haven't explained the problem clearly, I will explain it one more time with some screen shots.

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I think I have understood what you are trying to do, but a block diagram would help clarify.

Cheers,

Dave